System and method for selecting optimal data transition types for clock and data recovery
US7308048B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jan 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery. This determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.