Self correcting data re-timing circuit and method
US7308060B1 · kind B1 · utility
20Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2003 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.