Method of managing a multi-bit cell flash memory with improved reliablility and performance
US7308525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Aug 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of storing data by providing a flash memory device including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory cells used for storing M bits per cell, the memory cells are allocated to a page of the memory. Second data bits are stored into other memory cells, the other memory cells used for storing N bits per cell are allocated to the page and upon storing of the first data bits and upon storing the second data bits, the page uses at the same time at least one of the memory cells with M bits per cell and at least one of the other memory cells with N bits per cell with N less than M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.