Latent error detection
US7308605B2 · kind B2 · utility
17Cited by
14References
39Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 20, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Mar 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1633
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.