Interleaver and device for decoding digital signals comprising such an interleaver
US7308618B2 · kind B2 · utility
1Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Dec 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.