Circuit design verification using checkpointing
US7308663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jun 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design verification method, comprising providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, M checkpointed splits, and N non-checkpointed splits; and executing the stimulus tree diagram, wherein said executing the stimulus tree diagram comprises, for i=1, . . . , M, executing an ith checkpointed split of the M checkpointed splits, wherein said executing the ith checkpointed split comprises (a) saving an ith context of an ith simulation environment in which said executing the stimulus tree diagram is performed; and (b) after said saving the ith context is performed, executing from the ith context along Pi paths of the stimulus tree diagram branching from the ith checkpointed split, wherein the ith checkpointed split is a Pi-way split, Pi being an integer greater than 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.