Ordering of high use program code segments using simulated annealing
US7308683B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, program product and method utilize a heuristic-based algorithm such as simulated annealing to order program code segments in a computer memory to provide improved computer performance in terms of memory access, e.g., by minimizing cache misses or other memory-related performance penalties that may be present in a multi-level memory architecture. Program code is ordered in a computer memory by selecting an ordering from among a plurality of orderings for a plurality of program code segments using a heuristic algorithm, and ordering the plurality of program code segments in a memory of a computer using the selected ordering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.