3-D readout-electronics packaging for high-bandwidth massively paralleled imager
US7309878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2004 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | May 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10158
Abstract
Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a “mirror cube”). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45° angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.