States encoding in multi-bit flash cells
US7310347B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Jun 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
N data bits are stored in ┌N/M┐ cells by programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies one of the following criteria: Either the number of threshold voltage comparisons needed to read all M bits sequentially is at most 1 more than the smallest such number, or the largest number of threshold voltage comparisons needed to read any bit is minimized, or the smallest number of threshold voltage comparisons needed to read any bit is minimized, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit statically is at most 1 more than the smallest such difference, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit dynamically is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.