Gate line drivers for active matrix displays
US7310402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Jun 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register in an amorphous-silicon gate driver comprises a pull-up transistor and two pull-down modules. The pull-up transistor produces a positive pulse when the clock signal is high and the gate of the pull-up transistor is also high. The gate of the pull-up transistor is pulled down to a negative voltage level Vss by two pull-down transistors in the pull-down modules. Each pull-down module also has a further pull-down transistor to keep the output terminal at Vss after the output pulse is produced. The two pull-down modules are operated in a cooperative manner so that each pull-down transistor is conducting approximately 50% of the time. The gates of the pull-down transistors are kept at a positive voltage level approximately 50% of the time and at Vss′ approximately 50% of the time with Vss′ being more negative than Vss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.