Method and apparatus for primary cache tag error handling
US7310709B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Dec 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary cache to the secondary cache. In response to the tag parity packet, each tag entry in the secondary cache that is associated with the parity error is invalidated. Upon receiving an acknowledgment of receipt of the tag parity packet, the primary cache functions to invalidate each tag entry in the primary cache that is associated with the parity error. Then, the secondary cache communicates data requested in the load instruction to the primary cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.