Apparatus and method for trace stream identification of a processor debug halt signal
US7310749B2 · kind B2 · utility
12Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2003 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a DEBUG HALT signal is generated in a target processor during a test procedure, a debug halt sync marker is generated in a program counter trace stream. The debug halt sync marker includes a plurality of packets, the packets identifying that the sync marker is the result of a DEBUG HALT signal. The packets also identify the program counter address at the time of the generation of the DEBUG HALT signal and relate the debug halt sync marker to a timing trace stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.