Error detection on programmable logic resources
US7310757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2002 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.