Method and apparatus for checking read errors with two cyclic redundancy check stages
US7310765B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Feb 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/29
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection circuit is configured to generate a first error detection sequence in a first order. The system includes a second error detection circuit. The second error detection circuit is configured to receive the first error detection sequence and an error sequence. The error sequence is received in a second order that is different from the first order when there is data with errors. The second error detection circuit is configured to generate a second error detection sequence that indicates whether the error sequence is generated correctly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.