Decoding block codes
US7310767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2004 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/618
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder receiving a length n soft input vector, creating a binary vector Y corresponding to the soft input vector, hard decoding each linear function Xi of Y and a test pattern Zi of one or more test patterns, wherein if the hard decoding is successful a codeword produced by the hard decoding of Xi is added to a set S, removing redundant codewords in S to form a reduced set S′ based on processing a number of errors found during the hard decoding and a guaranteed error correcting capability of the block code decode, and an extrinsic value estimator generating n soft outputs based on c estimated soft output values and (n-c) non-estimated soft output values wherein the c estimated soft output values are computed from one or more positions of soft input vector and one or more codewords in S′.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.