IC compaction system
US7310786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding electronic device, and the shape and position of each object within the cell layout represents the shape and position of the corresponding portion of IC material within the corresponding electronic device. When a dimension or position of an object within a cell's internal layout can be altered without affecting the behavior of the electronic device the cell describes, a device rule is created for that cell to indicate any constraint on that object's dimension or relative position. The IC layout is then compacted both by moving cell instances closer together, and also by altering internal layouts of cell instances in a manner consistent with their device rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.