Thin film transistor array panel and method for fabricating the same
US7312470B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Nov 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136236
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer. The data wire includes a data line, a source electrode connected to the data line, a drain electrode facing the source electrode and a data pad connected to one end of the data line. A passivation layer is formed on the gate insulating layer while exposing the data pad and a portion of the data line close to the data pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.