Methods and apparatus for improved memory access
US7313035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Jan 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.