Sense amplifier circuit and method
US7313041B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Dec 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device memory device (300) can include a sense amplifier (302) enabled according to a first sense signal (setn) and a second sense signal (setp). In a sense operation, a first sense signal (setn) can be driven to a first, below ground potential. Subsequently, in the same sense operation, the first sense signal (setn) can be raised and maintained at a ground potential. Such an approach can substantially eliminate a sense amplifier stall condition that can occur under low temperature and/or low voltage operation. According to another aspect of the embodiments, a more negative logical “0” value can be written back into the memory cell during an access and/or refresh operation. This more negative value is available due to the below ground level provided during a sense operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.