PAPR reduction method using bit reallocation
US7313195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2004 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Jan 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A PAPR reduction method using bit reallocation is disclosed, which is applied in a multi-carrier system. The lowest total transmission power P is achieved by a bit loading algorithm conditioned on the requirement of total D transmission bits per block. When the PAPR (peak to average power ratio) of the block is larger than a predetermined value A, the bit reallocation is performed to add Δd-bit transmitting data to one sub-carrier and subtract Δd-bit transmitting data from another sub-carrier, thereby continuing bit reallocation until the PAPR meets with the system requirement or an iteration number reaches a predetermined maximal number of iteration L.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.