Stable process induced correction bias circuitry for receivers on single-ended applications
US7313372B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Aug 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0296
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.