Galois field arithmetic unit for use within a processor
US7313583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2003 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Dec 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, a 1st operand and a 2nd operand. The bit size of the 1st and 2nd operands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the 1st and 2nd operands. The bit size of the corresponding portions of the 1st and 2nd operands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.