Inter-processor communication system for communication between processors
US7313641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Nov 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.