Vectorization in a SIMdD DSP architecture
US7313788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Dec 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture, computing a set of candidate configurations of resources required for vectorizing the data in the architecture, where the computing step includes configuring a vector pointer register of the architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of the architecture, selecting one of the candidates in accordance with predefined selection criteria, and implementing the selected vectorization configuration in the architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.