Wafer-level processing of chip-packaging compositions including bis-maleimides
US7314778B2 · kind B2 · utility
4Cited by
5References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Mar 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of packaging a microelectronic chip includes wafer-level application of a chip-packaging composition that includes a polymer of a bis-maleimide. A process includes wafer-level addition of the chip-packaging compositions that include adding particulate fillers to achieve a coefficient of thermal expansion of about 20 ppm/K. A computing system is also included that uses a microelectronic die that was processed with the bis-maleimide at the wafer level, before singulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.