Method and apparatus for polysilicon resistor formation
US7314829B2 · kind B2 · utility
4Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Aug 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention include implanting and annealing polysilicon lines to form a silicide blocking layer that may inhibit silicide formation. The silicide blocking layer may facilitate fabrication of polysilicon resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.