Method of forming a source/drain and a transistor employing the same

US7315051B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventor

• Shui-Ming Cheng · Baoshan, TW

Key dates

• Filing date: Feb 17, 2005
• Grant date: Jan 1, 2008
• Expiry date: Dec 9, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method of forming a source/drain having a reduced junction capacitance and a transistor employing the same. In one embodiment, the method of forming the source/drain includes forming a recess in a substrate adjacent a gate of the transistor and forming a deep doped region below a bottom surface of the recess. The method also includes epitaxially growing a semiconductor material within the recess and forming a lightly doped drain region adjacent the gate.