CMOS transistor and method of manufacturing the same
US7315063B2 · kind B2 · utility
4Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Feb 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.