Native high-voltage n-channel LDMOSFET in standard logic CMOS

US7315067B2 · kind B2 · utility

Assignee

• Impinj, Inc. · US

Inventor

• Bin Wang · Beijing, CN

Key dates

• Filing date: Jul 2, 2004
• Grant date: Jan 1, 2008
• Expiry date: Jul 9, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/661

Abstract

A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain terminal coupled to the second n+ doped region, a p+ doped region disposed in the substrate, a body terminal coupled to the p+ doped region, a dielectric layer disposed over the p− doped substrate and a portion of the n− well, a first trench disposed in the n− well, the trench filled with a dielectric material that is in contact with the dielectric layer, a second trench disposed at least partially in the n− well, the second trench filled with a dielectric material and isolating the second n+ region from the p+ region, and a gate partially or fully reversely doped with p+ implant (or an equivalent technique) and disposed over the dielectric layer and a portion of the first trench.