Low-noise sigma-delta frequency synthesizer
US7315601B2 · kind B2 · utility
2Cited by
12References
16Claims
0Family size
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Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Jul 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.