Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers
US7315879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Feb 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110a) connected to at least one of the Booth encoder cells (104a) and a plurality of Wallace tree cells (112a) connected to at least one of the Booth decoder cells (110a). Moreover, at least one first Wallace tree cell (112a1) or at least one first Booth decoder cell (110a1), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell (112a2) or at least one second Booth decoder cell (110a2), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module (100) includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.