CPU system, bus bridge, control method therefor, and computer system
US7315913B2 · kind B2 · utility
8Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2005 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Dec 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system having an arrangement that a CPU (101) connected to a bus (107) via bus bridge (103) and a CPU 102 connected to a bus (107) via bus bridge (104), when the bus bridge (103) receives a semaphore acquisition request from the CPU (101), it controls acquisition of a semaphore on the basis of a semi_out signal received from the bus bridge (104) and a priority order received via a signal line (112).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.