Phase error determination method and digital phase-locked loop system
US7315968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2006 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Dec 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.