Systems and methods for improved memory scan testability
US7315971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2005 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Nov 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.