Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface
US7316061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2003 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | May 2, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/30
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.