Strain enhanced ultra shallow junction formation
US7316960B2 · kind B2 · utility
19Cited by
4References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2004 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes introducing dopants to the substrate to form a source region and a drain region. A strained layer may be formed over the substrate after introducing the dopants, and an annealing process may be performed after forming the strained layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.