Method for manufacture of an epitaxial structural element layer sequence and optoelectronic semiconductor chip
US7317202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2004 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for fabricating an epitaxial component layer sequence based on a first III/V compound semiconductor material system with a first group V element on a substrate or a buffer layer, which comprises a material based on a second III/V compound semiconductor material system with a second group V element, which is different from the first group V element. At least one layer sequence with a first and a second III/V compound semiconductor material layer is applied to the substrate or to the buffer layer before the application of the epitaxial component layer sequence, the first and second III/V compound semiconductor material layers having different compositions from one another and containing both the first and the second group V elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.