N-domino register with accelerated non-discharge path
US7317339B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-charges a pre-charged node high when the symmetric clock signal is low and opens an evaluation window when the pulsed clock signal goes high, and pulls the pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The output stage provides an output signal based on states of the pre-charged node and a second preliminary output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.