Signal timing for I/O
US7317644B1 · kind B1 · utility
4Cited by
4References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 15, 2005 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Dec 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.