Predicted parallel branch slicer and slicing method thereof
US7317755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2003 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Oct 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03592
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A predicted parallel branch slicer for use in an adaptive decision feedback equalizer includes Mk adders commonly receiving a signal to be processed and respectively receiving Mk preset values, and performing respective addition operations to generate Mk output signals; Mk slicers in communication with the Mk adders, receiving and processing the Mk output signals to obtain Mk signals of Mk levels, respectively; a multiplexer in communication with the Mk slicers, receiving the signals of the Mk levels; and k delay units interconnected with one another in series and being in communication with the multiplexer, and generating k selection signals of different delay time in response to an output of the multiplexer, the selection signals being provided for the multiplexer to select one of the signals of the Mk levels to be outputted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.