Shift register circuit
US7317780B2 · kind B2 · utility
31Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2006 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | May 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.