Hardware assisted communication between processors
US7318120B2 · kind B2 · utility
11Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2004 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Jan 18, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99955
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.