Fault tolerant computer
US7318169B2 · kind B2 · utility
Inventor
Key dates
| Filing date | May 6, 2003 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | May 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.