Decoding method, decoding apparatus, and program to decode low density parity check codes
US7318186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2004 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | May 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6577
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P×P unit matrix, a quasi-unit matrix in which one or more 1s, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P×P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices. A check node calculator 302 simultaneously performs p check node calculations. A variable node calculator 304 simultaneously performs p variable node calculations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.