Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal display panel having the same
US7319240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2005 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Apr 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a transparent substrate, a switching element, an insulating layer and a pixel electrode. The switching element includes a gate electrode formed on the transparent substrate and connected to a gate line, a channel layer formed on the gate electrode and extended in a first direction, a source electrode formed on the transparent substrate and connected to a source line and a drain electrode formed on the channel layer to cover the channel layer. The insulating layer has a contact hole to partially expose the drain electrode and the transparent substrate. The pixel electrode is connected to the drain electrode through the contact hole. When the above array substrate is employed in a liquid crystal display panel, the array substrate reduces pixel defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.