Semiconductor device
US7319271B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2006 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Jan 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and a via formed by filling with a conductive material the inside of a wiring trench formed on the face side of a layer insulation film and a contact hole provided at a bottom portion of the wiring trench. The layer insulation films constituting the plurality of wiring layers are so configured that the layer insulation films are changed in the magnitude of mechanical strength alternately on a wiring layer basis in the lamination direction of the wiring layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.