Built-in memory current test circuit
US7319625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2006 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Jul 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.