Semiconductor memory device with a stacked-bank architecture and method for driving word lines of the same
US7319631B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2005 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Sep 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.