Apparatus and method for memory with bit swapping on the fly and testing
US7320100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2004 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Sep 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.