Fast parallel calculation of cyclic redundancy checks
US7320101B1 · kind B1 · utility
7Cited by
40References
18Claims
0Family size
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Inventor
Key dates
| Filing date | Aug 19, 2003 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Sep 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for the fast parallel calculation of CRCs. One embodiment provides a feedforward path that combines common terms to simplify input logic. Common expressions that appear in multiple terms in the feedforward path are implemented using logic gates that are shared by the multiple terms, thereby reducing logic complexity, fan-out, and gate delay. Another embodiment provides a CRC logic architecture having a feedback path that is able to use more than one clock cycle in its computation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.